SYNC=DISABLED, SSSDIS=SEND_START_AND_STOP_, CSRC=SYNCHRONOUS_SLAVE_MO, TSBYPASS=THE_INPUT_CLOCK_IS_S, CCCLR=CSCEN_IS_UNDER_SOFTW, FES=RXD_IS_SAMPLED_ON_TH, CSCEN=SCLK_CYCLES_ONLY_WHE
Synchronous mode control register.
| SYNC | Enables synchronous mode. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| CSRC | Clock source select. 0 (SYNCHRONOUS_SLAVE_MO): Synchronous slave mode (SCLK in) 1 (SYNCHRONOUS_MASTER_M): Synchronous master mode (SCLK out) |
| FES | Falling edge sampling. 0 (RXD_IS_SAMPLED_ON_TH): RxD is sampled on the rising edge of SCLK 1 (RXD_IS_SAMPLED_ON_TH): RxD is sampled on the falling edge of SCLK |
| TSBYPASS | Transmit synchronization bypass in synchronous slave mode. 0 (THE_INPUT_CLOCK_IS_S): The input clock is synchronized prior to being used in clock edge detection logic. 1 (THE_INPUT_CLOCK_IS_N): The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability. |
| CSCEN | Continuous master clock enable (used only when CSRC is 1) 0 (SCLK_CYCLES_ONLY_WHE): SCLK cycles only when characters are being sent on TxD 1 (SCLK_RUNS_CONTINUOUS): SCLK runs continuously (characters can be received on RxD independently from transmission on TxD) |
| SSSDIS | Start/stop bits 0 (SEND_START_AND_STOP_): Send start and stop bits as in other modes. 1 (NOSTARTSTOPBIT): Do not send start/stop bits. |
| CCCLR | Continuous clock clear 0 (CSCEN_IS_UNDER_SOFTW): CSCEN is under software control. 1 (HARDWARE_CLEARS_CSCE): Hardware clears CSCEN after each character is received. |
| RESERVED | Reserved. The value read from a reserved bit is not defined. |